Die/Wafer Sub-Micron Alignment Strategies for Semiconductor Device Integration

CMOS Semiconductor Manufacturing Integration on Sub-micron Gate Spacer

This paper describes the details of a novel manufacturing process integration of CMOS (Complementary Metal-Oxide-Semiconductor) transistor architecture, which is incorporated into a sub-micron logic technology on 300mm wafers. As the gate length is scaling down, the spacer design for CMOS transistor becomes increasingly important especially for high performance. Experimental manufacturing proce...

Simulation Study of Deep Sub-micron and Nanoscale Semiconductor Transistors

Active Electrostatic Discharge (ESD) Device for On-Chip ESD Protection in Sub-Quarter-Micron Complementary Metal-Oxide Semiconductor (CMOS) Process

A novel electrostatic discharge (ESD) protection device with a threshold voltage of 0V for complementary metal-oxide semiconductor (CMOS) integrated circuits in sub-quarter-micron CMOS technology is proposed. Quite different to the traditional ESD protection devices, such an active ESD device is originally standing in its turn-on state when the IC is zapped under ESD events. Therefore, such an ...

Strain In Semiconductor Nanowires And Device Integration

One-dimensional nanowires (NWs) are promising materials for future nanodevices owing to their small dimensions and novel properties. After ten years of materials optimization [1], it is now possible with the help of X-rays and synchrotron radiation to draw some preliminary conclusions about the structural requirements necessary to tune the physical properties of demanding devices in terms of st...

Integration and test strategies for semiconductor manufacturing equipment

The complexity of semiconductor manufacturing equipment is growing. This growth results in a complexity increase of the integration and test phase of these systems. Simply adding more test resources is not possible anymore, because of the cost involved. A better design of an integration and test strategy can help to optimize this hectic phase. However, methods to design and evaluate integration...